新一轮的FAB招聘开始了Job Opening Summary:
GF Operation:
--------------
Principle and above engineers for Process and Equipment for Etch/Clean Tech/Diff/Imp/TF/CMP/Litho/Metro
GF TD:
-------
TD TCAD MTS
TD BiCMOS Principle
TD Device Engineering (NVM) MTS and Principle
TD SPICE Modeling Manager
TD Logic MTS and Principle
SSMC:
------
Implant Manager (Process and Equipment)
Senior Process Development Engineer
Thin Film Equipment Engineer (CVD) * 1 position, Familiar with Applied HDP (8 inch), Preferably 1 month notice
Thin Film Equipment Engineer (PVD) * 1 position, Familiar with Endura (8 inch), Preferably 1 month notice
Diffusion Furnance Process Senior Engineer, 2-3 in TSMC is a must, development job scope
Product Engineer (eFlash, RF and EEPROM), prefer TSMC candidates
具体要求和职位介绍接下来会跟帖贴出来，有兴趣的筒子请发简历至usmrecruiting@gmail.com,标题注明要申请的职位。如果上诉没有您想要的职位，但是想换工作的话，也可以发送简历并注明想要的工作，一旦有满足您要求的职位空缺我会尽快的联系您！请注意目前我的业务范围只包括FAB的工作，其他行业暂时心有余而力不足，帮不到您。 =）
目前我是PART TIME的猎头，FULL TIME的孩子妈，所以只能在晚上宝宝睡了以后检查回复电邮。如不能及时回复还请见谅。[凡人 (2-14 22:54, Long long ago)]
[ 传统版 |
sForum ][登录后回复]1楼
GF OPERATION： Principle and above engineers for Process and Equipment[凡人 (2-14 22:58, Long long ago)] [ 传统版 | sForum ][登录后回复]2楼
(引用 凡人:GF OPERATION： Principle and above engineers for Process and Equipment)Section Manager (Etch)
[凡人 (2-14 23:24, Long long ago)]
[ 传统版 |
sForum ][登录后回复]3楼
(引用 凡人:GF OPERATION： Principle and above engineers for Process and Equipment)Equipment Senior Principal Engineer/ Principal Engineer-Etch/Clean Tech/Diff/Imp
[凡人 (2-14 23:28, Long long ago)]
[ 传统版 |
sForum ][登录后回复]4楼
汗，贴了无数次文字版一直有问题无法发帖，最后只能贴截图字比较小，大家将就看吧。我明天再继续，看能不能把文字版的顺利复制贴出来。今天太晚熬不住了，对不住大家了！ORZ[凡人 (2-14 23:36, Long long ago)] [ 传统版 | sForum ][登录后回复]5楼
请问这些职位都是要求有工作经验的吗？请问凡人姐姐，fresh grad 什么时候开始面试呢。年前这两家公司都投了简历。一直没有回音，是不是没希望了。我是材料专业的[游离的沼泽鱼 (2-15 19:32, Long long ago)] [ 传统版 | sForum ][登录后回复]6楼
(引用 游离的沼泽鱼:请问这些职位都是要求有工作经验的吗？请问凡人姐姐，fresh grad 什么时候开始面试呢。年前这两家公司都投了简历。一直没有回音，是不是�...)嗯，绝大部分都是要求有一定工作经验的通常通过猎头招聘的职位都是比较SENIOR LEVEL的，所以要求一定的工作经验。
某些职位FRESH可以申请的也会在招聘要求里面写清楚的，我之前贴过的那篇招聘帖里只有一个职位是写明了FRESH可以申请的。但是一般来说，JUNIOR ENGINEER LEVEL应届生也可以尝试。[凡人 (2-15 21:17, Long long ago)]
[ 传统版 |
sForum ][登录后回复]7楼
GF TD[凡人 (2-15 21:52, Long long ago)] [ 传统版 | sForum ][登录后回复]8楼
(引用 凡人:GF TD)TD TCAD MTS
Responsibilities:
Optimize CMOS and Bipolar process and device using TCAD simulations
Accelerate technology development and technology transfer using TCAD software for process and device simulations
Work closely with R&D device and process integration teams to evaluate physical and electrical experimental data
Work closely with Fab process integration teams to fit device and process to customer needs
Optimize process and device stability control using DOE (Design Of Experiments) and DFM (Design For Manufacturability) methodologies
Create and monitor timelines and plans for TCAD development work
Generate methodologies for continuous improvement of TCAD calibration and simulations
Investigate new models for process and device simulations
Compare different vendor software for speed, accuracy and efficiency
Contribute to Globalfoundries Intellectual Property (Patents)
Link with Academic Institution for publications, and or joined projects participate to the elaboration of calibration methodology
Requirements
PHD/Masters/Degree in Electrical/Electronics/Microelectronics Engineering/Material Science with microelectronics module/Physics with semi-conductor background/ Chemistry with semi-conductor background or experience
4 or more years in Academic Institution with or without industrial experience with a direct involvement in process and/or device modeling and a very good record in publications (eg, IEDM-VLSI-IEEE journals)
5 or more years of relevant fab experience preferred with involvement in process and device modeling
6 or more years of relevant experience in TCAD company with a strong collaboration with industrial partners
Good interpersonal and communication skills.
Good analytical skills/presentation skills.
Essential in using MS Office/UNIX/LINUX and familiar with SUN and PC environment
Good in using Tsuprem4,Medici,TWB as well as Sentaurus Process and Device and
Sentaurus WorkBench as well as atomistic process software.
Must be a team player and capable to adapt quickly to new environment
Must show ownership in conducting his/her carrier path
Must show a strong leadership and be capable to motivate a team
[凡人 (2-15 21:53, Long long ago)]
[ 传统版 |
sForum ][登录后回复]9楼
(引用 凡人:GF TD)TD Device Engineering (NVM) MTS and Principle
Responsibilities:
Design of embedded NVM devices, with a focus on reliability improvement
Detailed characterization of embedded NVM cells, including design of test structures and development and implementation of test methodologies
Process development of embedded NVM technology, working closely with Process Integration and Module Development
Requirements
Masters Degree in Electronics and Electrical Engineering
Minimum 5 years of relevant working experience
Experience in detailed electrical characterization of NVM devices
Strong grasp of NVM reliability physics and experience in improving NVM reliability
FEOL Integration experience
Strong interest in device and process physics
Aptitude for design and optimization
Ability and desire to work in a team
Good communication and interpersonal skills
[凡人 (2-15 21:55, Long long ago)]
[ 传统版 |
sForum ][登录后回复]10楼
(引用 凡人:GF TD)TD SPICE Modeling Manager
Responsibilities
To lead and manage SPICE measurement group to enhance the measurement capability to be able to handle more challenges and needs in both VAS and advanced technology offering
To enhance the group’s initiative in the area of test structure development for SPICE modeling and characterization which is expected to gain complexity with more advanced features
Requirements
Master Degree in Electronic Engineer
12 Years of relevant experience
Experience in managing team working in device measurement / characterization / modeling / test structure generation and enhancement
Knowledge in semiconductor device physics/ test chip development/ characterization and modeling
DC, CV measurement and characterisation expertise
Test Pattern Improvement and layout of structures
Create & monitor timelines & plans for SPICE measurement and characterization projects to be completed on time
Knowledge of major measurement and modeling tools
A good role model, well-respected to the team and cross-functional groups
Guide and mentor engineers to achieve their goals in line with cross-functional and corporate goals
Good interpersonal and communication skill, tactful, resourceful, possess initiative, pleasant personality
[凡人 (2-15 21:55, Long long ago)]
[ 传统版 |
sForum ][登录后回复]11楼
(引用 凡人:GF TD)TD Logic MTS and Principle
Responsibilities
Design of transistors using TCAD and process experiments to meet performance and reliability requirements
Benchmarking of device architecture and performance
Design and analysis of experiments
Development of new test and device design methodologies
Electrical test structure specification
Electrical characterization of transistors
Mentoring and training of junior engineers/associate engineers
Requirements
PhD or Masters in Electrical / Electronics Engineering or equivalent
Field of specialization: Microelectronics
At least 5 years developing advanced transistors
Familiarity with TCAD tools
Experience in detailed electrical characterization of devices
FEOL Integration experience would be an advantage
Strong interest in device and process physics
Aptitude for design and optimization
Ability and desire to work in a team
Good communication and interpersonal skills
[凡人 (2-15 21:56, Long long ago)]
[ 传统版 |
sForum ][登录后回复]12楼
(引用 凡人:GF TD)TD BiCMOS Principle嗯，这个不需要具体要求了，不知道BICOMS的可以跳过了。
Principle至少要六年经验，可以上班的话我自己都想试试了。=P
[凡人 (2-15 22:00, Long long ago)]
[ 传统版 |
sForum ][登录后回复]13楼
SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧[凡人 (2-15 22:01, Long long ago)] [ 传统版 | sForum ][登录后回复]14楼
(引用 凡人:SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧)Product Engineer (eFlash, RF and EEPROM), prefer TSMC candidatesResponsibilities
Job Purpose:
To work closely with customers to provide product engineering support for all products
Technical:
Resolve yield, quality and reliability issues in the qualification of new devices
Conduct product yield analyses to identify root cause of wafer sort and final test failures
Coordinate test program development activities and changes between customers, vendors and test house
Support cost reduction through yield improvement and fab in resolving excursion
Work with Customers on product low yield disposition
Perform electrical and physical failure analysis to isolate fail location
Innovation & Quality:
Participate in continuous improvement programs
Safety:
Compliance to safety, discipline and housekeeping rules
Leadership:
Mentor to junior engineers & associates
Requirements
Master / Degree in Electrical / Electronics Engineering or Science in Physics/ Chemistry / Material Sciences
4 – 8 years product and/or test engineering, failure analysis or process-integration experience
Experience in IC process, yield engineering or design will be an added advantage
In depth knowledge of semiconductor device physics, electrical & electronics engineering fundamentals & wafer fabrication processes
Strong analytical & problem solving skills
[凡人 (2-15 22:04, Long long ago)]
[ 传统版 |
sForum ][登录后回复]15楼
(引用 凡人:SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧)Diffusion Furnance Process Senior Engineer(2-3 years in TSMC is a must)Responsibilities
To establish systems/guidance in developing, sustenance and improvement of process capability indices to exceed/meet operations goals.
Perform shift duties to support production when requested
Monitor process performance indices on qualified processes and establish good controls to maintain process performance
Troubleshoot out-of-control situations and process issues and put corrective actions in place
Start-up new equipment processes which involves process characterization and development
Work as a team with equipment, integration and manufacturing engineers and external customers to meet modules objectives
Establish work procedures, corrective actions and preventions.
Oversee all Special Test Request, Non Conformance Review, Engineering Abnormal Report status and follow-up actions
Manage/drive vendors performance to meet/exceed equipment KPI and goals
Requirements
MSc/ Degree in Electrical / Electronics / Mechanical / Mechatronics / Microelectronics / Physics / Science /Chemical Engineering or equivalent
2-5 years semiconductor wafer fab operational experience with technical expertise in related area as Process Engineer.
At least 7 years direct experience in semiconductor for Diploma holders.
Expert semiconductor wafer fabrication process knowledge
Team performance management knowledge
In-depth experience in related process
Team leader experience
Supervisory & coaching skills
Vendor management skills
Good project management skills
Strong problem solving skills
Good analytical skills
SPC and DOE knowledge
[凡人 (2-15 22:10, Long long ago)]
[ 传统版 |
sForum ][登录后回复]16楼
(引用 凡人:SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧)Equipment Senior Engineer (CVD/PVD each 1 position)Thin Film Equipment Engineer (CVD) * 1 position, Familiar with Applied HDP (8 inch), Preferably 1 month notice
Thin Film Equipment Engineer (PVD) * 1 position, Familiar with Endura (8 inch), Preferably 1 month notice
Responsibilities
To establish systems/guidance in sustenance and improvement of all equipment performance indices to exceed/meet operations goals
Perform shift duties for scheduled equipment preventive maintenance (PM) and troubleshoot equipment-related problems to minimize equipment downtime when requested.
Execute new equipment start-up, from facilities hook-up, vendor start-up, to acceptance of equipment for production.
Coordinate with process, integration and manufacturing engineers to ensure work is carried out efficiently to meet module objectives.
Establish stock levels of essential equipment spares, consumables and other equipment-related expenditures to support equipment maintenance based on forecasted manufacturing volume.
Manage/drive vendors’ performance to meet/exceed equipment KPI and goals.
Document PM/recovery procedures and best known methods for equipment to allow more efficient troubleshooting.
Provide and maintain preventive maintenance specifications for equipment to meet ISO requirements and Quality Systems.
Initiate, organize and lead task-force for short term problem solving and long term continuous improvement
Participate in continuous improvement programs to optimize equipment utilization, cost of maintenance and implement equipment improvement projects to upkeep capabilities and reliabilities of equipment
Requirements
MSc/ Degree in Electrical / Electronics / Mechanical / Mechatronics / Microelectronics / Materials Science / Chemical Engineering or equivalent
2-5 years semiconductor wafer fab operational experience with technical expertise in related area as equipment engineer.
Relevant Field Service experience of over 5 years may also be considered.
At least 7 years direct experience in semiconductor for Diploma holders.
Expert semiconductor wafer fabrication equipment/ process knowledge
In depth experience in related equipments
Team performance management knowledge
Strong equipment trouble shooting skills
In-depth experience in related equipments
Team leader experience
Supervisory & coaching skills
Vendor management skills
Strong problem solving skills
Strong project management skills[凡人 (2-15 22:13, Long long ago)]
[ 传统版 |
sForum ][登录后回复]17楼
(引用 凡人:SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧)Senior Process Development EngineerResponsibilities
Develop & qualify custom or derivative processes to customer
Integrate of all modules' processes and the respective derivatives.
Run DOE to optimize process integration and to determine the process spec
Resolve all process integration issues by ensuring all window checks are done on critical process steps identified in FMEA
Identify and correct all ET related problems that may affect seamless production
Write Engg lot report for every new device & experiment
To prepare proper transfer documents for Integration
Monitor inline lot movement to ensure that there is no process issues with lot & meet timeline
Maintain good Cpk for ET and monitor inline SPC parameters for assigned process
Requirements
Masters / PhD in Engineering, major in Electrical, Electronics, Microelectronics, Material science, Materials engineering, or Physics
2-5 years fab experience in Integration / Device Physics
Good communication and presentation skills
Able to take pressure under time-constrained situations
[凡人 (2-15 22:15, Long long ago)]
[ 传统版 |
sForum ][登录后回复]18楼
(引用 凡人:SSMC的职位空缺这家花红听闻还是不错的，不过有的职位要求很变态。。。大家自己看吧)Implant Manager (Process and Equipment)[凡人 (2-15 22:16, Long long ago)] [ 传统版 | sForum ][登录后回复]19楼
今天网络很给面子，顺利贴完了，请资深的SEMICON筒子们多多支持！=）[凡人 (2-15 22:19, Long long ago)] [ 传统版 | sForum ][登录后回复]20楼
华新中文网 版权所有