这个配置为什么superPI要2分多钟？怎么想都不太可能啊。。按理说1分钟都不用。。
北京中关村配的，可能的原因哪位高手能分析一下么？谢谢
Name AMD Athlon XP
Code Name Barton
Specification AMD Athlon(tm) XP 2600+
Family / Model / Stepping 6 A 0
Extended Family / Model 7 A
Package Socket A
Technology 0.13 ?/small>
Supported Instructions Sets MMX, Extended MMX, 3DNow!, Extended 3DNow!, SSE
CPU Clock Speed 1916.8 MHz
Clock multiplier x 11.5
Front Side Bus Frequency 166.7 MHz
Bus Speed 333.4 MHz
L1 Data Cache 64 KBytes, 2-way set associative, 64 Bytes line size
L1 Instruction Cache 64 KBytes, 2-way set associative, 64 Bytes line size
L2 Cache 512 KBytes, 16-way set associative, 64 Bytes line size
L2 Speed 1916.8 MHz (Full)
L2 Location On Chip
L2 Data Prefetch Logic yes
L2 Bus Width 64 bits
Memory
DRAM Type DDR-SDRAM
DRAM Size 512 MBytes
DRAM Frequency 200.0 MHz
FSB:DRAM 5:6
CAS# Latency 2.0 clocks
RAS# to CAS# 3 clocks
RAS# Precharge 3 clocks
Cycle Time (TRAS) 8 clocks
Name AMD Athlon XP
Code Name Barton
Specification AMD Athlon(tm) XP 2600+
Family / Model / Stepping 6 A 0
Extended Family / Model 7 A
Package Socket A
Technology 0.13 ?/small>
Supported Instructions Sets MMX, Extended MMX, 3DNow!, Extended 3DNow!, SSE
CPU Clock Speed 1916.8 MHz
Clock multiplier x 11.5
Front Side Bus Frequency 166.7 MHz
Bus Speed 333.4 MHz
L1 Data Cache 64 KBytes, 2-way set associative, 64 Bytes line size
L1 Instruction Cache 64 KBytes, 2-way set associative, 64 Bytes line size
L2 Cache 512 KBytes, 16-way set associative, 64 Bytes line size
L2 Speed 1916.8 MHz (Full)
L2 Location On Chip
L2 Data Prefetch Logic yes
L2 Bus Width 64 bits
Memory
DRAM Type DDR-SDRAM
DRAM Size 512 MBytes
DRAM Frequency 200.0 MHz
FSB:DRAM 5:6
CAS# Latency 2.0 clocks
RAS# to CAS# 3 clocks
RAS# Precharge 3 clocks
Cycle Time (TRAS) 8 clocks
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